1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of branch prediction within data processing systems.
2. Description of the Prior Art
As instruction pipeline depths have become greater, the penalty for incorrectly predicting the program flow has increased. When program flow is incorrectly predicted, then instructions within the instruction pipeline will need to be flushed and the correct instructions fetched. This consumes many processing cycles and wastes energy.
In order to accurately predict branch behaviour it is known to provide one or more branch prediction mechanisms within a data processing apparatus to direct the prefetching and supply of instructions to the instruction pipeline(s). These branch prediction mechanisms can be highly complex and require a large number of gates and a significant amount of power to operate. The typical approach to increasing branch prediction accuracy is to increase these branch prediction mechanisms in size and complexity, e.g. increasing the size of a branch target address cache, increasing the size of a global history table etc. The incremental increase in prediction accuracy associated with increasing the resources allocated to the branch predictors reduces as the branch predictors increase in size and complexity. A significant proportion of a high performance data processing integrated circuit may be consumed by sophisticated branch prediction mechanisms.